In mobile electronic devices, namely devices such as laptop computers having a limited power supply (e.g., battery-powered), personal data assistants (PDAs) and cell phones, reducing the power consumption of such devices is important in order to extend the amount of time the devices may be operated on a limited amount of energy. Typically, these types of devices include a display screen for displaying image data. In some particular applications run on these devices, the applications generating image data, the image data displayed is static; that is, the same image is constantly displayed. Examples of such applications may include Windows® desktop for a computer or applications such as word processing programs, e-mail programs, and other similar applications where the displayed image data may often times be constant or static.
During display of the static data discussed above, no processing of image data is performed by processing devices, such as a central processing unit or a graphic processing unit, and, consequently, no image data is written to memory locations storing the display image data. Nonetheless, in computing systems, such as the devices enumerated above, display image data is typically read by a display controller from the memory locations under the direction of a memory controller controlling read and write accesses of the memory locations. That is, the display controller is a real time client in that the image data is continuously fetched from memory for displaying images on a display medium. In particular, the image data is typically fetched from the memory in advance of display and temporarily buffered or stored in a line buffer contained within the display controller prior to display in order to ensure the data will be displayed on time. The line buffer is configured to store a number of entries or lines of image data.
Although display image data may be static, because the memory controller continues to access memory at the request of the display controller, power consumption is still relatively high, despite the lack of processing of data and memory writes. In light of the amounts of power consumed during display of static screen images, it is known in the art to employ various schemes in order to attempt to reduce the power consumption when static images are being displayed on a screen, taking advantage of the constancy of the data in memory. Such schemes include, for example, lowering the clock frequency of the processor (i.e., the memory client) during periods of a static condition of image data stored in the memory. Another approach includes lowering the core power rail voltage (i.e., the voltage of the processor or memory client). Further schemes known in the art include dynamic clock branches in the memory controller, which involves shutting off different clocking branches to reduce the amount of switching or clock gating, thereby lowering power. In particular, CMOS circuits, whose power consumption is directly proportional to the amount of switching, are typically utilized in memory controllers and, thus, reducing the amount of switching of these CMOS circuits helps to reduce the power consumption.
Moreover, in particular memories, such as double data rate (DDR) synchronous dynamic RAM memories (DDR SDRAM), industry standards governing the construction of such devices provide power saving functionalities within the memory devices. In particular, the JEDEC Solid State Technology Association has developed specifications such as the DDR2 SDRAM specification (JESD 79-2A, January 2004) providing at least three different functionalities for power reduction. These three functionalities are active power down, pre-charged power down, and self-refresh. The active power down operation, in particular, affects a lower power state for the memory device while pages are open and being accessed from banks within the memory device. The pre-charge power down operation affects a low power state of the memory when particular pages are closed. Particularly in instances where image data is static, pre-charge power down operation has typically been used to reduce power consumption. Although the active power down and pre-charge power down operations provided by the JEDEC standard serve to reduce power, these modes of operation still require that a memory controller drive clock signals to the memory device, the signals communicated over the memory interface. Since these clock signals are typically implemented with CMOS circuitry, the switching required to drive the clock signals consumes high amounts of power.
The third power saving operation provided by the JEDEC standard mentioned above is self-refresh operation. In this mode, the memory device itself serves to refresh the dynamic RAM circuits within the memory device. When a memory device is in this mode, the memory controller no longer needs to drive clock signals to the memory. A disadvantage with self-refresh mode, however, is the high latency when bringing the memory device out of the self-refresh mode. Thus, this mode is typically not used to save power when the display device is active, especially for memories used to store image data to be displayed by a display controller because of the high latency to bring back the memory out of self-refresh.